Showing 7 results for Cmos
A. Saberkari, S. B. Shokouhi,
Volume 1, Issue 4 (10-2005)
Abstract
In this paper, an imaging chip for acquiring range information using by
0.35 μm CMOS technology and 5V power supply has been described. The system can
extract range information without any mechanical movement and all the signal processing
is done on the chip. All of the image sensors and mixed-signal processors are integrated in
the chip. The design range is 1.5m-10m with 18 scales.
P. M. Farahabadi, H. Miar-Naimi, A. Ebrahimzadeh,
Volume 5, Issue 1 (3-2009)
Abstract
New equations are proposed for frequency and amplitude of a ring oscillator.
The method is general enough to be used for all types of delay stages. Using exact largesignal
circuit analysis, closed form equations for estimating the frequency and amplitude of
a high frequency ring oscillator are derived as an example. The method takes into account
the effect of various parasitic capacitors to have better accuracy. Based on the loop gain of
the ring, the transistors may only be in saturation or experience cutoff and triode regions.
The analysis considers all of the above mentioned scenarios respectively and gives distinct
equations. The validity of the resulted equations is verified through simulations using
TSMC 0.18 µm CMOS process. Simulation results show the better accuracy of the
proposed method compared with others.
S. R. Talebiyan, S. Hosseini-Khayat,
Volume 5, Issue 3 (9-2009)
Abstract
A fast low-power 1-bit full adder circuit suitable for nano-scale CMOS implementation is presented. Out of the three modules in a common full-adder circuit, we have replaced one with a new design, and optimized another one, all with the goal to reduce the static power consumption. The design has been simulated and evaluated using the 65 nm PTM models.
M. Piry, M. Khanjani Moaf, P. Amiri,
Volume 10, Issue 1 (3-2014)
Abstract
Class-AB circuits, which are able to deal with currents several orders of magnitude larger than their quiescent current, are good candidates for low-power and high slew-rate analog design. This paper presents a novel topology of a class AB flipped voltage follower (FVF) that has better slew rate and the same power consumption as the conventional class-AB FVF buffer previously presented in literature. It is thus suitable for low-voltage and low-power stages requiring low bias currents. These buffers have been simulated using 0.5µm CMOS Technology models provided by IBM. The buffer consumes 20µA from a 0.9V supply and has a bandwidth of 50MHz with a 18pF load. It has a slew rate of 9.8V/µs and power consumption of 42µw
S. Ejdehakosh, M. A. Karami,
Volume 15, Issue 4 (12-2019)
Abstract
This work presents a dual-junction, single-photon avalanche diode (SPAD) with electrical μ-lens designed and simulated in 90 nm standard complementary metal oxide semiconductor (CMOS) technology. The evaluated structure can collect the photons impinging beneath the pixel guard ring, as well as the pixel active area. The fill factor of the SPAD increases from 12.5% to 42% in comparison with similar works on the same technology, according to new charge collections. Although the designed SPAD suffers from high dark count rate (DCR of 300kHz at 0.17V excess bias at room temperature) due to high amount of tunneling which was predicted in previous similar works, it still can be used in different applications such as random number generators and charged particle positioning pixels.
P. Gupta, S. K. Jana,
Volume 17, Issue 2 (6-2021)
Abstract
The advancement in the integrated circuit design has developed the demand for low voltage portable analog devices in the market. This demand has increased the requirement of the low-power RF transceiver. A low-power phase lock loop (PLL) is always desirable to fulfill the need for a low power RF transceiver. This paper deals with the designing of the low power transconductance- capacitance (Gm-C) based loop filter with the help of the gate-driven quasi bloating Bulk (GD-QFB) MOS technique. The GD-QFB MOS-based operational transconductance amplifier (OTA) has been proposed with a high dc gain of 82.41 dB and less power consumption of 188.72 µW. Further, Gm-C based active filter has been designed with the help of the proposed GD-QFB OTA. The simulation results of Gm-C filter attain a -3 dB cut-off frequency of 59.08 MHz and power consumption of 188.31µW at the supply voltage of 1V. The proposed Gm-C filter is suitable for the designing of 1-3 GHz low power PLL.
H. Ghonoodi, M. Hadjmohammadi,
Volume 17, Issue 4 (12-2021)
Abstract
In this paper a novel design is presented for a dual-band LC oscillator, using an analytical approach. The core of the proposed circuit contains a cross-coupled CMOS LC oscillator with two serried LC tanks so that the inductors of these tanks have mutual inductance. There are some switches in the circuit that directly changes mutual inductance to produce two different frequencies. This technique increases the oscillation amplitude in the same power consumption that leads to the decrement of phase noise. In other words, using two serried LC tank compensates the injected phase noise from switches. The symmetrical structure is another advantage of the presented design that makes it possible to be used in multiphase oscillator. To assess the quality of the proposed circuit, a dual-band quadrature LC oscillator has been designed to oscillate at 3.6 GHz and 6.4 GHz with 1.5 V supply and 1 mA current consumption, with TSMC 0.18 CMOS practical model. Lastly, simulation results confirm the correctness of analytical results and high proficiency of the proposed design.
